The subject matter disclosed herein relates to semiconductor devices, and more specifically, to a sputtering process for forming a metal layer on a semiconductor device.
Power conversion devices are widely used throughout modern electrical systems to convert electrical power from one form to another form for consumption by a load. Many power electronics systems utilize various semiconductor devices and components, such as thyristors, diodes, and various types of transistors (e.g., metal-oxide-semiconductor field-effect transistor (MOSFETs), insulated gate bipolar transistors (IGBTs), and other suitable transistors), in this power conversion process. Some semiconductor devices may include a plurality of cells (e.g., transistor cells) formed on a semiconductor substrate. During the fabrication of such semiconductor devices, one or more metal layers may be deposited on a surface of the semiconductor device (e.g., metallization) to electrically connect features of the semiconductor device to a lead of an external package. Generally, the metal layers are deposited over a surface of the semiconductor device that includes one or more steps, such as trenches and openings (e.g., contact vias), formed between different layers of the semiconductor device. The degree to which the metal layers cover the step features, which may be referred to as the step coverage, may affect the reliability of the semiconductor device.
For many power electronics systems, increasing the cell density of semiconductor devices may be desirable to increase the current capacity and/or to decrease the footprint of the semiconductor devices. Accordingly, it may be desirable to decrease the dimensions of the cells to enable more cells to be packed into the same area. However, decreasing the cell dimensions may cause challenges in the fabrication of semiconductor devices and their associated cells. In particular, as cell dimensions decrease, the dimensions of the trenches and openings in the stepped surface of the semiconductor device generally decrease, which may increase the difficulty in obtaining adequate step coverage, reducing the reliability of the semiconductor device.
In one embodiment, a semiconductor device includes a semiconductor device layer including a first surface and a second surface. The semiconductor device also includes a plurality of gate electrodes disposed on the first surface of the semiconductor device layer, wherein the plurality of gate electrodes are spaced apart from one another. Additionally, the semiconductor device includes a plurality of contact regions disposed in the first surface of the semiconductor device layer, wherein each contact region of the plurality of contact regions is disposed between adjacent gate electrodes of the plurality of gate electrodes. The semiconductor device also includes a dielectric layer disposed on and adjacent to each gate electrode of the plurality of electrodes. The dielectric layer includes a plurality of openings, wherein each opening of the plurality of openings is disposed over a contact region of the plurality of contact regions. Further, the semiconductor device includes an aluminum layer disposed on the dielectric layer. The aluminum layer extends into each opening of the plurality of openings of the dielectric layer such that the aluminum layer is disposed on the plurality of contact regions of the semiconductor device layer. A step coverage of the aluminum layer in each opening of the plurality of openings is greater than or equal to approximately 75%.
In one embodiment, a method includes sputtering a first portion of an aluminum layer on a surface of the semiconductor device disposed in a sputtering chamber. Sputtering the first portion of the aluminum layer includes supplying power to an aluminum target disposed in the sputtering chamber at a first power level using a target power supply, supplying a bias voltage to the semiconductor device at a first bias voltage level using a bias voltage supply, and supplying a sputtering gas into the sputtering chamber using a sputtering gas supply. Additionally, the method includes sputtering a second portion of the aluminum layer adjacent to the first portion of the aluminum layer. Sputtering the second portion of the aluminum layer includes supplying the power to the aluminum target at a second power level greater than the first power level using the target power supply, supplying the bias voltage to the semiconductor device at a second bias voltage level using the bias voltage supply, and supplying the sputtering gas into the sputtering chamber using the sputtering gas supply. Further, the method includes sputtering a third portion of the aluminum layer adjacent to the second portion of the aluminum layer. Sputtering the third portion of the aluminum layer includes supplying the power to the aluminum target to a third power level greater than the first power level using the target power supply, electrically floating the semiconductor device, and supplying the sputtering gas into the sputtering chamber using the sputtering gas supply.
In one embodiment, a power conversion system includes a semiconductor device including a semiconductor device layer having a first conductivity type. The semiconductor device layer has a first surface and a second surface. The semiconductor device also includes a plurality of source regions adjacent to the first surface, wherein each source region of the plurality of source regions has the first conductivity type. Additionally, the semiconductor device includes a plurality of well regions implanted adjacent to the first surface and the plurality of source regions, wherein each well region of the plurality of regions has a second conductivity type. Further, the semiconductor device includes a plurality of dielectric layers disposed on the first surface and electrically isolating a plurality of gate electrodes of the semiconductor device. The semiconductor device also includes a semiconductor substrate layer disposed adjacent to the second surface and a drain pad disposed adjacent to the semiconductor substrate layer. The semiconductor device also includes a gate pad disposed on the plurality of dielectric layers. The gate pad extends through one or more first openings formed through the plurality of dielectric layers to electrically connect to the plurality of gate electrodes of the semiconductor device. Further, the semiconductor device includes a source pad disposed on the plurality of dielectric layers and electrically isolated from the gate pad. The source pad extends through one or more second openings formed through the plurality of dielectric layers to electrically connect to a plurality of contact regions disposed in the first surface of the semiconductor device layer. Each contact region comprises a portion of at least one source region of the plurality of source regions, a portion of at least one well region of the plurality of well regions, or both. The source pad includes an aluminum layer that extends at least partially into the one or more second openings, and a step coverage of the aluminum layer in the one or more second openings is greater than or equal to approximately 80%.